REG.I.PERIOD_ITERS       10

This property contains the period for the operational current regulation algorithm. With 10 it means a sampling rate of 1kHz which is normally fine for our application and that Auxpole 1 and 2 could reach a value of 100Hz.

VS.ACT_DELAY_ITERS     2.0000000E+00

This property contains the pure delay in iterations between the calculation of the actuation by the RST regulator and the power converter starting to change the firing pattern. Typically between 1 and 2.

REG.I.INTERNAL.PURE_DELAY_PERIODS 0.0000000E+00

This property allows the pure delay to be optionally specified. If set to zero, the internal algorithm will calculate the pure delay using the following algorithm:

PURE_DELAY_PERIODS = (VS.ACT_DELAY_ITERS + VS_RSP_DELAY_ITERS + MEAS_DELAY_ITERS) / REG.I.PERIOD_ITERS + FIRING_DELAY

Start with a value set manually to 0.3

The pure delay is very important for the internal RST synthesis algorithm:

0.0 -> 0.4 : Algorithm 1 – Real dead-beat PII with TRACK_DELAY_PERIODS = 1

0.4 -> 1.0 : Algorithm 2 – Pseudo-dead-beat PII with TRACK_DELAY_PERIODS = 1 + PURE_DELAY_PERIODS

1.0 -> 1.4 : Algorithm 3 – Real dead-beat PII with TRACK_DELAY_PERIODS = 2 period

1.4 -> 2.0 : Algorithm 4 – Pseudo-dead-beat PII with TRACK_DELAY_PERIODS = 2 + PURE_DELAY_PERIODS

2.0 -> 2.4 : Algorithm 5 – Real dead-beat PII with TRACK_DELAY_PERIODS = 3

Typically around 50-70Hz bandwidth should be possible. This is around 10-20 times lower than the voltage loop bandwidth

REG.I.INTERNAL.AUXPOLE1_HZ 2.0000000E+01,4.0000000E+01,1.0000000E+05,2.0000000E+02
REG.I.INTERNAL.AUXPOLES2_HZ               2.0000000E+01,2.0000000E+01,2.0000000E+01,2.0000000E+02

To calculate the RST regulator, the VS transfer fonction shall be approximated by a second order system : it is used not only in SIMULATION mode but also in real mode

VS.SIM.Z              6.9999999E-01

VS.SIM.BANDWIDTH      1.0000000E+03